1. Field of the Invention
The present invention relates to a design support device and a design support system used in design and development processes for logical circuit systems such as semiconductor integrated circuits and the like, and more particularly, it relates to a design support device and a design support system for estimating performances of logic circuits, for allocating positions or locations of modules, and for designing areas and timings of modules before logical synthesis operation or before a logical gate design and a layout design which are performed during a register transfer level to a gate design level.
2. Description of the Prior Art
Recently, there is a method of counting the number of actual logic gates and of investigating delay time periods of signals transferred between the actual logic gates that are generated by a logical synthesis operation as a method of counting the number of gates and of calculating delay time periods between gates by using a Hardware Description Language (hereinafter referred to as "HDL") in a Register Transfer Level (hereinafter referred to as "RTL") which is commonly used as a design language for a logic design of semiconductor integrated circuits and the like. However, this method has a drawback that it requires a long time period to perform the logical synthesis operation.
In addition, there is a floor planner performing a floor-plan operation for allocating modules by using a logic gates, namely a net list, in a gate design level after the completion of the logic synthesis operation and the like, as an allocating method of allocating each module in a semiconductor chip. However, this floor planner executes the floor plan operation by using results which have already been converted into the logic gate level. Therefore, it is difficult to allocate modules on a semiconductor chip during the RTL design level performed before the gate design level.
As described above, in the prior art, it is not performed to estimate the performance of logic circuits and not to allocate modules on a semiconductor chip during the RTL design level which is the stage before the gate design level. The logical synthesis operation described above performed before the gate design level must be repeated many times or repeated manually when a designer does not satisfy the result synthesized logically during the RTL design level. Thus, there is the drawback in the prior art that the number of design iterations becomes high.
In addition, there is a drawback that the number of design iterations becomes high because it is difficult to converge the design operation when the result of a placement operation and a wiring operation become bad, specifically, when the length of wiring becomes long and when the delay time of a signal transfer in a module becomes long in the placement and wiring operation for logic gate circuits obtained by the logical synthesis operation performed by automatic processes or manually.
Furthermore, a designer estimates the number of gates in each module, a delay time in each module, and roughly allocates the position of each module on a semiconductor chip in the RTL design level based on the experience of the designer when the design for a semiconductor integrated circuit in a large circuit size is performed. However, the designer can not design and estimate accurately the number of gates and the delay time. Moreover, there is no design circumstances such as a top down design method in the prior art in which the logical synthesis operation and the layout operation can be performed by using the estimation result roughly designed by the designer. Accordingly, the number of design iterations is increased.
Thus, it is not disclosed in the prior art to estimate the performance of logic circuits and to allocate modules on a semiconductor chip during the RTL design level. Therefore the number of design iterations is increased and the logical synthesis operation and the layout operation must be repeated many times when a designer does not satisfy the result of the logical synthesis operation or the layout operation, so that the efficiency of the design operation becomes low and it takes a long time to execute the design operation of semiconductor integrated circuits.